Modern nonvolatile memories include EEPROM devices, such as flash memories that employ a floating gate structure. Memory cells within these devices use channel-hot electrons for programming from the drain side and use Fowler-Nordheim tunneling for erasure from the source side. The gate structure for these devices is typically a stack configuration comprising a floating gate and a control gate separated by an insulation layer.
An existing process used to isolate adjacent conventional flash memory cells is the LOCOS isolation process. Flash memories with LOCOS isolation employ a self-aligned source etch (SAS) and ion implantation to form a continuous source line. The continuous source line normally connects the source of each flash memory cell in a column of the memory and is used for erasing the cells of the memory. To form a continuous source line, a conductive path is created between the source region of adjacent cells so as to create an electrical connection between the adjacent source regions. Preferably, the electrical path through the isolation region is a low resistance path.
More recently, another isolation process has been used to create the isolation region between flash memory cells, especially for embedded memory applications. This process is known as shallow trench isolation (STI), so named because the process results in narrow rectangular trenches between adjacent memory cells. Because of the steepness of the trench walls created by the shallow trench isolation process, it is difficult to use ion implantation in the isolation region, yet maintain a self-aligned source region with a low sheet resistance. The effectiveness of the ion implantation process depends upon the sidewall slope and depth of the trench and control of that process will be difficult to achieve.
To overcome the difficulties of using ion implantation to dope the sidewalls of trench isolation regions, tilt angle ion implantation has been attempted. Unfortunately, tilt angle ion implantation may require the use of multiple energy levels, making the resulting process difficult to control. Also, several tilt angles may need to be used to properly dope the sidewalls of the trench isolation region. The semiconductor processing equipment used for ion implantation must be adjusted for each tilt angle employed in the process. Such adjustment can be time consuming and may require processing to be stopped temporarily for such adjustment to take place. Tilt angle ion implantation may thus substantially increase the cost of flash memory structures in integrated circuits employing shallow trench isolation.
Accordingly, a need has arisen for a processing method which provides for the doping of a trench isolation region so as to form a low resistance continuous source line in a floating gate memory structure.